View CH7012_1141974.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

chrontel 201-0000-042 rev. 1.1, 9/29/2000 1 CH7012a chrontel CH7012 tv output device features ? tv output supporting up to 1024x768 graphics resolutions ? programmable digital interface supports rgb and ycrcb ? truescale tm rendering engine supports underscan in all tv output resolutions ? enhanced text sharpness and adaptive flicker removal with up to 7 lines of filtering ? support for all ntsc and pal formats ? provides cvbs, s-video and scart (rgb) outputs ? tv connection detect ? programmable power management ? 10-bit video dac outputs ? fully programmable through serial port ? complete windows and dos driver support ? low voltage interface support to graphics device ? offered in a 64-pin lqfp package general description the CH7012 is a display controller device which accepts a digital graphics input signal, and encodes and transmits data to a tv output (analog composite, s- video or rgb). the device accepts data over one 12-bit wide variable voltage data port which supports five different data formats including rgb and ycrcb. the tv-out processor will perform non-interlace to interlace conversion with scaling and flicker filters, and encode the data into any of the ntsc or pal video standards. the scaling and flicker filter is adaptive and programmable to enable superior text display. eight graphics resolutions are supported up to 1024 by 768 with full vertical and horizontal underscan capability in all modes. a high accuracy low jitter phase locked loop is integrated to create outstanding video quality. support is provided for rgb bypass mode which enables driving a vga crt with the input data. figure 1: functional block diagram pll rgb-yuv converter system clock yuv-rgb converter digital input interface serial port register & control block line memory true scale scaling & deflickering engine timing & sync generator ntsc/pal encoder & filters d [11:0] pixel data xclk/xclk* h v xi/fin xo p-out sc sd reset* bco iset csync gpio[1:0] y/r cvbs/b c/g cvbs four 10-bit dac?s
chrontel CH7012a 2 201-0000-042 rev. 1.1, 9/29/2000 pin descriptions package diagram figure 2: 64-pin lqfp dvddv c / h sync y / g c / r cvbs iset vdd gnd gnd agnd xi / fin xo avdd gpio[1] gpio[0] as dgnd agnd avdd nc nc nc nc nc nc nc nc nc nc nc nc nc nc dgnd sd sc reset* nc dvdd vref dvdd agnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 26 27 28 29 30 31 32 17 18 19 20 21 22 23 24 25 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 cvbs / b chrontel xclk xclk* d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] dgnd dvdd h v nc bco p-out CH7012
201-0000-042 rev. 1.1, 9/29/2000 3 chrontel CH7012a table 1: pin description 64-pin lqfp # pins type symbol description 3 1 in vref reference voltage input the vref pin inputs a reference voltage of dvddv / 2. the signal is derived externally through a resistor divider and decoupling capacitor, and will be used as a reference level for data, sync and clock inputs. 4 1 in/out h horizontal sync input / output when the syo bit is low, this pin accepts a horizontal sync input for use with the input data. the amplitude will be 0 to dvddv, and the vref signal is used as the threshold level. when the syo bit is high, the device will output a horizontal sync pulse, 64 pixels wide. the output is driven from the dvdd. this output is only for use with the tv-out function. 5 1 in/out v vertical sync input / output when the syo bit is low, this pin accepts a vertical sync input for use with the input data. the amplitude will be 0 to dvddv, and the vref signal is used as the threshold level. when the syo bit is high, the device will output a vertical sync pulse one line wide. the output is driven from the dvdd supply. this output is only for use with the tv-out function. 7 2 in/out gpio[1] general purpose input - output[1] (internal pull-up) this pin provides a general purpose i/o controlled via the serial port bus. the internal pull-up will be to the dvdd supply. 8 2 in/out gpio[0] general purpose input - output[0] (internal pull-up) this pin provides a general purpose i/o controlled via the serial port bus. this allows an external switch to be used to select ntsc or pal at power-up. the internal pull-up will be to the dvdd supply. 10 1 in as address select (internal pull-up) this pin determines the serial port address of the device (1,1,1,0,1,as*,as). 13 1 in reset* reset * input (internal pull-up) when this pin is low, the device is held in the power-on reset condition. when this pin is high, reset is controlled through the serial port register. 14 1 in/out sd serial data input / output this pin functions as the serial data pin of the serial port interface, and uses the dvdd supply. 15 1 in sc serial clock input this pin functions as the clock pin of the serial port interface, and uses the dvdd supply. 35 1 in iset current set resistor input this pin sets the dac current. a 140 ohm resistor should be connected between this pin and gnd (dac ground) using short and wide traces.
chrontel CH7012a 4 201-0000-042 rev. 1.1, 9/29/2000 64-pin lqfp # pins type symbol description 36 1 out cvbs composite video this pin outputs a composite video signal capable of driving a 75 ohm doubly terminated load. 37 1 out y/g luma / green output this pin outputs a selectable video signal. the output is designed to drive a 75 ohm doubly terminated load. the output can be selected to be s-video luminance or green . 38 1 out c/r chroma / red output this pin outputs a selectable video signal. the output is designed to drive a 75 ohm doubly terminated load. the output can be selected to be s-video chrominance or red. 39 1 out cvbs/b composite video / blue output this pin outputs a selectable video signal. the output is designed to drive a 75 ohm doubly terminated load. the output can be selected to be composite video or blue. 42 1 in xi / fin crystal input / external reference input a parallel resonance 14.31818mhz crystal ( + 20 ppm) should be attached between this pin and xo. however, an external clock can drive the xi/fin input. 43 1 in xo crystal output a parallel resonance 14.31818mhz crystal ( + 20 ppm) should be attached between this pin and xi / fin. however, if an external cmos clock is attached to xi/fin, xo should be left open. 46 1 out p-out pixel clock output when the CH7012 is operating as a vga to tv encoder in master clock mode, this pin provides a pixel clock signal to the vga controller which is used as a reference frequency. the output is selectable between 1x or 2x of the pixel clock frequency. the output driver is driven from the dvddv supply. this output has a programmable tri-state. the capacitive loading on this pin should be kept to a minimum. 47 1 out bco buffered clock output this output pin provides a buffered clock output, driven by the dvdd supply. the output clock can be selected using the bco register. 48 1 out c/h sync composite / horizontal sync output this pin can be selected to output a tv composite sync, tv horizontal sync, or a buffered version of the vga horizontal sync. the output is driven from the dvdd supply. 50 ? 55, 58 ? 63 12 in d[11] - d[0] data[11] through data[0] inputs these pins accept the 12 data inputs from a digital video port of a graphics controller. the levels are 0 to dvddv, and the vref signal is used as the threshold level. table 1: pin description
201-0000-042 rev. 1.1, 9/29/2000 5 chrontel CH7012a 64-pin lqfp # pins type symbol description 57, 56 2 in xclk, xclk* external clock inputs these inputs form a differential clock signal input to the CH7012 for use with the h, v, de and d[11:0] data. if differential clocks are not available, the xclk* input should be connected to vref. the output clocks from this pad cell are able to have their polarities reversed under the control of the mcp bit. 2, 9, 19, 21, 23, 24, 25, 27, 28, 30, 31 11 nc no connect 1, 12, 49 3 power dvdd digital supply voltage (3.3v) 6, 11, 64 3 power dgnd digital ground 45 1 power dvddv i/o supply voltage (3.3v to 1.1v) 23, 29 2 power nc no connect 20, 26, 32 3 power nc no connect 18, 44 2 power avdd pll supply voltage (3.3v) 16, 17, 41 3 power agnd pll ground 33 1 power vdd dac supply voltage (3.3v) 34, 40 2 power gnd dac ground table 1: pin description
chrontel CH7012a 6 201-0000-042 rev. 1.1, 9/29/2000 modes of operation the CH7012 is capable of being operated as a vga to tv encoder. descriptions of the encoder operating modes, with a block diagram of the data flow within the device is shown below. tv output in tv output mode, multiplexed input data, sync and clock signals are input to the CH7012 from the graphics controller?s digital output port. a p-out clock can be output as a frequency reference to the graphics controller, which is recommended to ensure accurate frequency generation. horizontal and vertical sync signals are normally set to the CH7012 from the graphics controller, but can be output to the graphics controller as an option. data will be 2x multiplexed, and the xclk clock signal can be 1x or 2x times the pixel rate. the input data will be encoded into the selected video standard, and output from the video dac?s. the modes supported for tv output are shown in the table below, and a block diagram of the CH7012 is shown on the following page. 1 these dvd modes operate with interlaced input, scan conversion and flicker filter are bypassed. 2 these dvd modes operate with non-interlaced input, scan conversion is not bypassed. table 2: tv output modes graphics resolution active aspect ratio pixel aspect ratio tv output standard scaling ratios 512x384 4:3 1:1 pal 5/4, 1/1 512x384 4:3 1:1 ntsc 5/4, 1/1 720x400 4:3 1.35:1.00 pal 5/4, 1/1 720x400 4:3 1.35:1.00 ntsc 5/4, 1/1 640x400 8:5 1:1 pal 5/4, 1/1 640x400 8:5 1:1 ntsc 5/4, 1/1, 7/8 640x480 4:3 1:1 pal 5/4, 1/1, 5/6 640x480 4:3 1:1 ntsc 1/1, 7/8, 5/6 720x480 1 4:3 9:8 ntsc 1/1 720x480 2 4:3 9:8 ntsc 1/1, 7/8, 5/6 720x576 1 4:3 15:12 pal 1/1 720x576 2 4:3 15:12 pal 1/1, 5/6, 5/7 800x600 4:3 1:1 pal 1/1, 5/6, 5/7 800x600 4:3 1:1 ntsc 3/4, 7/10, 5/8 1024x768 4:3 1:1 pal 5/7, 5/8, 5/9 1024x768 4:3 1:1 ntsc 5/8, 5/9, 1/2
201-0000-042 rev. 1.1, 9/29/2000 7 chrontel CH7012a figure 3: tv output modes xclk,xclk* serial port control d[11:0] h,v data latch, demux 2 12 h,v latch clock driver as sc sd vref gpio[1:0] reset* xi/fin,xo cvbs (dac0) c (dac 2) y (dac 1) p-out four 10-bit dac's bco c/h sync iset scaling scan conv flicker filt tv encode tv-dll timing cvbs (dac3) 2 2 24 3 24 24
chrontel CH7012a 8 201-0000-042 rev. 1.1, 9/29/2000 input interface two distinct methods of transferring data to the CH7012 are described. they are: ? multiplexed data, clock input at 1x pixel rate ? multiplexed data, clock input at 2x pixel rate for the multiplexed data, clock at 1x pixel rate the data applied to the CH7012 is latched with both edges of the clock (also referred to as dual-edge transfer mode). for the multiplexed data, clock at 2x pixel rate the data applied to the CH7012 is latched with one edge of the clock. the polarity of the pixel clock can be reversed under serial port control. input clock and data timing diagram the figure below shows the timing diagram for input data and clocks. the first xclk/xclk* waveform represents the input clock for the multiplexed data, clock at 2x pixel rate method. the second xclk/xclk* waveform represents the input clock for the multiplexed data, clock at 1x pixel rate method. figure 4: interface timing 1 d[11:0], h, v de times measured when input equals vref+100mv on rising edges, vref-100mv on falling edges. table 3: interface timing symbol parameter min max unit v oh output high level of interface signals dvddv - 0.2 dvddv + 0.2 v v ol output low level of interface signals -0.2 0.2 v t1 1 d[11:0], h, v & de to xclk = xclk* delay (setup time) tbd ns t2 1 xclk = xclk* to d[11:0], h, v & de delay (hold time) tbd ns dvddv digital i/o supply voltage 1.1 ? 5% 3.3 + 5% v d[11:0] xclk/ xclk* h v de 64 p-out v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol t1 t2 t2 t1 1 vga line xclk/ xclk* v oh v ol
201-0000-042 rev. 1.1, 9/29/2000 9 chrontel CH7012a input clock and data formats the 12 data inputs support 5 different multiplexed data formats, each of which can be used with a 1x clock latching data on both clock edges, or a 2x clock latching data with a single edge. the data received by the CH7012 can be used to drive the vga to tv encoder or directly drive the dac?s. the multiplexed input data formats are (idf[2:0]): idf description 0 12-bit multiplexed rgb input (24-bit color), (multiplex scheme 1) 1 12-bit multiplexed rgb2 input (24-bit color), (multiplex scheme 2) 2 8-bit multiplexed rgb input (16-bit color, 565) 3 8-bit multiplexed rgb input (15-bit color, 555) 4 8-bit multiplexed ycrcb input (24-bit color), (y, cr and cb are multipl exed) for multiplexed input data formats, either both transitions of the xclk/xclk* clock pair, or each rising or falling edge of the clock pair (depending upon mcp bit, rising refers to a rising edge on the xclk signal, a falling edge on the xclk* signal) will latch data from the graphics chip. the multiplexed input data formats are shown in the figures below. the pixel data bus represents a 12-bit or 8-bit multiplexed data stream, which contains either rgb or ycrcb formatted data. the input data rate is 2x the pixel rate, and each pair of pn values (eg; p0a and p0b) will contain a complete pixel encoded as shown in the tables below. it is assumed that the first clock cycle following the leading edge of the incoming horizontal sync signal contains the first word (pxa) of a pixel, if an active pixel was present immediately following the horizontal sync. this does not mean that active data should immediately follow the horizontal sync, however. when the input is a ycrcb data stream the color-difference data will be transmitted at half the data rate of the luminance data, with the sequence being set as cb, y, cr, y, where cb0,y0,cr0 refers to co-sited luminance and color-difference samples and the following y1 byte refers to the next luminance sample, per ccir-656 standards (the clock frequency is dependent upon the current mode, and is not 27mhz as specified in ccir-656). all non-active pixels should be 0 in rgb formats, and 16 for y and 128 for crcb in ycrcb formats.
chrontel CH7012a 10 201-0000-042 rev. 1.1, 9/29/2000 figure 5: multiplexed input data formats (idf = 0, 1) d[11:0] hs xclk (2x) p1a p0a p2a p1b p0b p2b sav the following data is latched for idf = 0 the following data is latched for idf = 1 xclk (1x) p0b[11:4] p0b[3:0], p0a[11:8] p0a[7:0] p1b[11:4] p1a[7:0] p2b[11:4] p2a[7:0] p1b[3:0], p1a[11:8] p2b[3:0], p2a[11:8] p0b[11:7], p0b[3:1] p0b[6:4], p0a[11:9], p0b[0], p0a[3] p0a[8:4], p0a[2:0] p1b[11:7], p1b[3:1] p1b[6:4], p1a[11:9], p1b[0], p1a[3] p1a[8:4], p1a[2:0] p2b[11:7] p2b[3:1] p2a[8:4] p2a[2:0] p[7:0] (blue data) p[15:8] (green data) p[23:16] (red data) p[7:0] (blue data) p[15:8] (green data) p[23:16] (red data)
201-0000-042 rev. 1.1, 9/29/2000 11 chrontel CH7012a figure 6: multiplexed input data formats (idf = 2, 3, 4) d[11:0] hs xclk (2x) p1a p0a p2a p1b p0b p2b sav p0b[11:7] p0b[6:4], p0a[11:9] p0a[8:4] the following data is latched for idf = 2 the following data is latched for idf = 3 the following data is latched for idf = 4 xclk (1x) p1b[11:7] p1a[8:4] p2b[11:7] p2a[8:4] gnd p0b[7:0] p0a[7:0] gnd p1b[7:0] p1a[7:0] gnd p2a[7:0] p1b[6:4], p1a[11:9] p2b[6:4], p2a[11:9] p2b[7:0] cra (internal signal) p[7:3] (blue data) p[15:10] (green data) p[23:19] (red data) p[7:3] (blue data) p[15:11] (green data) p[23:19] (red data) p[7:0] (ignored) p[15:8] (crcb data) p[23:16] (y data) p0b[10:6] p0b[5:4], p0a[11:9] p0a[8:4] p1b[10:6] p1a[8:4] p2b[10:6] p2a[8:4] p1b[5:4], p1a[11:9] p2b[5:4], p2a[11:9]
chrontel CH7012a 12 201-0000-042 rev. 1.1, 9/29/2000 table 4: multiplexed input data formats (idf = 0, 1) idf = format = 0 12-bit rgb (12-12) 1 12-bit rgb (12-12) pixel # p0a p0b p1a p1b p0a p0b p1a p1b bus data d[11] g0[3] r0[7] g1[3] r1[7] g0[4] r0[7] g1[4] r1[7] d[10] g0[2] r0[6] g1[2] r1[6] g0[3] r0[6] g1[3] r1[6] d[9] g0[1] r0[5] g1[1] r1[5] g0[2] r0[5] g1[2] r1[5] d[8] g0[0] r0[4] g1[0] r1[4] b0[7] r0[4] b1[7] r1[4] d[7] b0[7] r0[3] b1[7] r1[3] b0[6] r0[3] b1[6] r1[3] d[6] b0[6] r0[2] b1[6] r1[2] b0[5] g0[7] b1[5] g1[7] d[5] b0[5] r0[1] b1[5] r1[1] b0[4] g0[6] b1[4] g1[6] d[4] b0[4] r0[0] b1[4] r1[0] b0[3] g0[5] b1[3] g1[5] d[3] b0[3] g0[7] b1[3] g1[7] g0[0] r0[2] g1[0] r1[2] d[2] b0[2] g0[6] b1[2] g1[6] b0[2] r0[1] b1[2] r1[1] d[1] b0[1] g0[5] b1[1] g1[5] b0[1] r0[0] b1[1] r1[0] d[0] b0[0] g0[4] b1[0] g1[4] b0[0] g0[1] b1[0] g1[1] table 5: multiplexed input data formats (idf = 2, 3) idf = format = 2 rgb 5-6-5 3 rgb 5-5-5 pixel # p0a p0b p1a p1b p0a p0b p1a p1b bus data d[11] g0[4] r0[7] g1[4] r1[7] g0[5] x g1[5] x d[10] g0[3] r0[6] g1[3] r1[6] g0[4] r0[7] g1[4] r1[7] d[9] g0[2] r0[5] g1[2] r1[5] g0[3] r0[6] g1[3] r1[6] d[8] b0[7] r0[4] b1[7] r1[4] b0[7] r0[5] b1[7] r1[5] d[7] b0[6] r0[3] b1[6] r1[3] b0[6] r0[4] b1[6] r1[4] d[6] b0[5] g0[7] b1[5] g1[7] b0[5] r0[3] b1[5] r1[3] d[5] b0[4] g0[6] b1[4] g1[6] b0[4] g0[7] b1[4] g1[7] d[4] b0[3] g0[5] b1[3] g1[5] b0[3] g0[6] b1[3] g1[6] table 6: multiplexed input data formats (idf = 4) idf = format = 4 ycrcb 8-bit pixel # p0a p0b p1a p1b p2a p2b p3a p3b bus data d[7] cb0[7] y0[7] cr0[7] y1[7] cb2[7] y2[7] cr2[7] y3[7] d[6] cb0[6] y0[6] cr0[6] y1[6] cb2[6] y2[6] cr2[6] y3[6] d[5] cb0[5] y0[5] cr0[5] y1[5] cb2[5] y2[5] cr2[5] y3[5] d[4] cb0[4] y0[4] cr0[4] y1[4] cb2[4] y2[4] cr2[4] y3[4] d[3] cb0[3] y0[3] cr0[3] y1[3] cb2[3] y2[3] cr2[3] y3[3] d[2] cb0[2] y0[2] cr0[2] y1[2] cb2[2] y2[2] cr2[2] y3[2] d[1] cb0[1] y0[1] cr0[1] y1[1] cb2[1] y2[1] cr2[1] y3[1] d[0] cb0[0] y0[0] cr0[0] y1[0] cb2[0] y2[0] cr2[0] y3[0]
201-0000-042 rev. 1.1, 9/29/2000 13 chrontel CH7012a when idf = 4 (ycrcb mode), the data inputs can also be used to transmit sync information to the device. in this mode, the embedded sync will follow the vip2 convention, and the first byte of the ?video timing reference code? will be assumed to occur when a cb sample would occur, if the video stream was continuous. this is shown below: i n this mode, the s[7..0] byte contains the following data: s[6] = f = 1 during field 2, 0 during field 1 s[5] = v = 1 during field blanking, 0 elsewhere s[4] = h = 1 during eav (synchronization reference at the end of active video) 0 during sav (synchronization reference at the start of active video) bits s[7] and s[3..0] are ignored. table 7: embedded sync idf = format = 4 ycrcb 8-bit pixel # p0a p0b p1a p1b p2a p2b p3a p3b bus data dx[7] ff 00 00 s[7] cb2[7] y2[7] cr2[7] y3[7] dx[6] ff 00 00 s[6] cb2[6] y2[6] cr2[6] y3[6] dx[5] ff 00 00 s[5] cb2[5] y2[5] cr2[5] y3[5] dx[4] ff 00 00 s[4] cb2[4] y2[4] cr2[4] y3[4] dx[3] ff 00 00 s[3] cb2[3] y2[3] cr2[3] y3[3] dx[2] ff 00 00 s[2] cb2[2] y2[2] cr2[2] y3[2] dx[1] ff 00 00 s[1] cb2[1] y2[1] cr2[1] y3[1] dx[0] ff 00 00 s[0] cb2[0] y2[0] cr2[0] y3[0]
chrontel CH7012a 14 201-0000-042 rev. 1.1, 9/29/2000 ntsc and pal operation composite and s-video outputs are supported in either ntsc or pal format. the general parameters used to characterize these outputs are listed in table 9 and shown in figure 7 . (see figures 10 through 15 for illustrations of composite and s-video output waveforms). 1. durations vary slightly in different modes due to the different clock frequencies used. 2. active video and black (f, g, h) times vary greatly due to different scaling ratios used in different modes. 3. black times (f and h) vary with position controls. figure 7: ntsc / pal composite output table 8. ntsc/pal composite output timing parameters (in m s) symbol description level (mv) duration (us) ntsc pal ntsc pal a front porch 287 300 1.49 - 1.51 1.48 - 1.51 b horizontal sync 0 0 4.69 - 4.72 4.69 - 4.71 c breezeway 287 300 0.59 - 0.61 0.88 - 0.92 d color burst 287 300 2.50 - 2.53 2.24 - 2.26 e back porch 287 300 1.55 - 1.61 2.62 - 2.71 f black 340 300 0.00 - 7.50 0.00 - 8.67 g active video 340 300 37.66 - 52.67 34.68 - 52.01 h black 340 300 0.00 - 7.50 0.00 - 8.67 a b c d e f g h
201-0000-042 rev. 1.1, 9/29/2000 15 chrontel CH7012a figure 8: interlaced ntsc video timing 520 521 522 523 524 525 1 2 3 4 5 6 7 258 259 260 261 262 263 264 265 266 267 268 269 272 start of vsync analog field 1 analog field 2 8 9 270 271 520 521 522 523 524 525 1 2 3 4 5 6 7 258 259 260 261 262 263 264 265 266 267 268 269 272 start of vsync analog field 1 analog field 2 8 9 270 271 520 521 522 523 524 525 1 2 3 4 5 6 7 258 259 260 261 262 263 264 265 266 267 268 269 272 start of vsync analog field 1 analog field 2 8 9 270 271 pre-equalizing pulse interval reference sub-carrier phase color field 1 line vertical interval vertical sync pulse interva l post-equalizing pulse interval start of field 1 start of field 2 reference sub-carrier phase color field 2 reference sub-carrier phase color field 3 reference sub-carrier phase color field 4 start of field 3 start of field 4 t 1 +v t 2 +v t 3 +v 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275
chrontel CH7012a 16 201-0000-042 rev. 1.1, 9/29/2000 figure 9: interlaced pal video timing 621 622 623 624 625 1 2 3 4 5 6 7 620 621 622 623 624 625 1 2 3 4 5 6 7 620 309 310 311 312 313 314 315 316 317 318 319 320 323 308 322 309 310 311 312 313 314 315 316 317 318 319 320 308 start of vsync analog field 1 analog field 2 analog field 3 analog field 4 burst blanking pal switch = 0, +v component burst phase = reference phase = 135 relative to u pal switch = 1, - v component burst phase = reference phase + 90 = 225 relative to u 8 9 10 321 8 9 10 323 322 321 621 622 623 624 625 1 2 3 4 5 6 7 620 621 622 623 624 625 1 2 3 4 5 6 7 620 309 310 311 312 313 314 315 316 317 318 319 320 323 308 322 309 310 311 312 313 314 315 316 317 318 319 320 308 start of vsync analog field 1 analog field 2 analog field 3 analog field 4 burst blanking pal switch = 0, +v component burst phase = reference phase = 135 relative to u pal switch = 1, - v component burst phase = reference phase + 90 = 225 relative to u 8 9 10 321 8 9 10 323 322 321 i n t e r v a l s 4 3 2 1
201-0000-042 rev. 1.1, 9/29/2000 17 chrontel CH7012a figure 10: ntsc y (luminance) output waveform (dacg = 0) figure 11: pal y (luminance) video output waveform (dacg = 1) color bars: w h i t e y e ll o w c ya n m a g e n t a g r ee n r e d b l u e b l ack color/level ma v white 26.66 1.000 yellow 24.66 0.925 cyan 21.37 0.801 green 19.37 0.726 magenta 16.22 0.608 red 14.22 0.533 blue 11.08 0.415 black 9.08 0.340 blank 7.65 0.287 sync 0.00 0.000 color bars: w h i t e y e ll o w c ya n m a g e n t a g r ee n r e d b l u e b l ack color/level ma v white 26.75 1.003 yellow 24.62 0.923 cyan 21.11 0.792 green 18.98 0.712 magenta 15.62 0.586 red 13.49 0.506 blue 10.14 0.380 blank/ black 8.00 0.300 sync 0.00 0.000
chrontel CH7012a 18 201-0000-042 rev. 1.1, 9/29/2000 figure 12: ntsc c (chrominance) video output waveform (dacg = 0) figure 13: pal c (chrominance) video output waveform (dacg = 1) color bars: w h i t e y e ll o w c ya n m a g e n t a g r ee n r e d b l u e b l ack color/level ma v cyan/red 25.80 0.968 green/magenta 25.01 0.938 yellow/blue 22.44 0.842 peak burst 18.08 0.678 blank 14.29 0.536 yellow/blue 6.15 0.230 green/magenta 3.57 0.134 cyan/red 2.79 0.105 peak burst 10.51 0.394 3.579545 mhz color burst (9 cycles) color bars: w h i t e y e ll o w c ya n m a g e n t a g r ee n r e d b l u e b l ack color/level ma v cyan/red 27.51 1.032 green/magenta 26.68 1.000 yellow/blue 23.93 0.897 peak burst 19.21 0.720 blank 15.24 0.572 yellow/blue 6.56 0.246 green/magenta 3.81 0.143 cyan/red 2.97 0.111 peak burst 11.28 0.423 4.433619 mhz color burst (10 cycles)
201-0000-042 rev. 1.1, 9/29/2000 19 chrontel CH7012a figure 14: composite ntsc video output waveform (dacg = 0) figure 15: composite pal video output waveform (dacg = 1) color/level ma v peak chrome 32.88 1.233 white 26.66 1.000 sync 0.00 0.000 peak burst 11.44 0.429 black 9.08 0.340 blank 7.65 0.281 peak burst 4.45 0.145 color bars: w h i t e y e ll o w c ya n m a g e n t a g r ee n r e d b l u e b l ack 3.579545 mhz color burst (9 cycles) color/level ma v peak chrome 33.31 1.249 white 26.75 1.003 sync 0.00 0.000 peak burst 11.97 0.449 blank/black 8.00 0.300 peak burst 4.04 0.151 color bars: w h i t e y e ll o w c ya n m a g e n t a g r ee n r e d b l u e b l ack 4.433619 mhz color burst (10 cycles)
chrontel CH7012a 20 201-0000-042 rev. 1.1, 9/29/2000 register control the CH7012 is controlled via an serial port control. the serial port bus uses only the sc clock to latch data into registers, and does not use any internally generated clocks so that the device can be written to in all power down modes. the device retains all register states . the CH7012 contains a total of 37 registers for user control. a listing of non-macrovision control bits are listed below with a brief description of each. non-macrovision control registers map the non-macrovision controls are listed below, divided into three sections: general controls, input / output controls and vga to tv controls. a register map and register description follows. general controls resetib software serial port reset resetdb software datapath reset pd[5:0] power down controls (tvd, dacpd[3:0], full, partial) vid[7:0] version id register did[7:0] device id register tstp[1:0] enable/select test pattern generation (color bar, ramp) input/output controls xcm xclk 1x, 2x select xcmd[7:0] delay adjust between xclk and d[11:0] mcp xclk polarity control pcm p-out 1x, 2x select poutp p-out clock polarity poute p-out enable hpie, hpie2 hot plug detect interrupt enable hpir hot plug detect interrupt reset idf[2:0] input data format ibs input buffer select des decode embedded sync (tv-out data only) syo h/v sync direction control (for tv-out modes only) vsp v sync polarity control (sync polarity to tmds tm links is not changed) hsp h sync polarity control (sync polarity to tmds tm links is not changed) term[5:0] termination detect/check (tmds tm link, dact3, dact2, dact1, dact0, sense) bcoen enable bco output bco[2:0] select output signal for bco pin bcop bco polarity gpiol[1:0] read or write level for gpio pins goenb[1:0] direction control for gpio pins synco[1:0] enables/selects sync output for scart and bypass modes dacg[1:0] dac gain control dacbp dac bypass xosc[2:0] crystal oscillator adjustments
201-0000-042 rev. 1.1, 9/29/2000 21 chrontel CH7012a tv-out controls ir[2:0] input data resolution (when used for tv-out) vos[1:0] tv-out video standard sr[2:0] tv-out scaling ratio cff[1:0] chroma flicker filter setting yfft[1:0] luma text enhancement flicker filter setting yffnt[1:0] luma flicker filter setting (non-text) cvbwb cvbs dac receives black&white (s-video luminance) signal cbw chroma video bandwidth ysv[1:0] s-video luma bandwidth ycv[1:0] composite video luma bandwidth te[2:0] text enhancement (sharpness) cfrb chroma sub-carrier free run (bar) control m/s* tv-out pll reference input control sav [8:0] horizontal start of active video (delay from leading edge of h2 sync to active video) blck[7:0] tv-out black level control hp[8:0] tv-out horizontal position control vp[8:0] tv-out vertical position control vof tv-out video format (s-video & composite, rgb) ce[2:0] tv-out contrast enhancement plltvm[8:0] tv-out pll m divider plltvn[9:0] tv-out pll n divider fsci[32:0] sub-carrier generation increment value (when aciv=0) civen calculated sub-carrier enable (was called aciv) civc[1:0] calculated sub-carrier control (hysteresis, civ[25:0] calculated sub-carrier increment value read out civpn select pal-n when in a civ mode mem[2:0] memory sense amp reference adjust vbid vertical blanking interval defeat pllcpi tv-out pll charge pump current control pllcap tv-out capacitor control
chrontel CH7012a 22 201-0000-042 rev. 1.1, 9/29/2000 registers read/write regarding the CH7012 registers read/write operation, please see applications note an-42 for details. non-macrovision control registers description all register bits not defined in the register map are reserved bits, and should be left at the default value. table 9 shows the ch7009 non-macrovision register map. the details are described as follows: table 9: serial port register map w/o macrovision register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h ir2 ir1 ir0 vos1 vos0 sr2 sr1 sr0 01h vof0 cff1 cff0 yfft1 yfft0 yffnt1 yffnt0 02h vbid cfrb cvbwb cbw ysv1 ysv0 ycv1 ycv0 03h sav8 hp8 vp8 te2 te1 te0 04h sav7 sav6 sav5 sav4 sav3 sav2 sav1 sav0 05h hp7 hp6 hp5 hp4 hp3 hp2 hp1 hp0 06h vp7 vp6 vp5 vp4 vp3 vp2 vp1 vp0 07h bl7 bl6 bl5 bl4 bl3 bl2 bl1 bl0 08h ce2 ce1 ce0 09h mem2 mem1 mem0 n9 n8 m8 pllcpi pllcap 0ah m7 m6 m5 m4 m3 m2 m1 m0 0bh n7 n6 n5 n4 n3 n2 n1 n0 0ch fsci31 fsci30 fsci29 fsci28 fsci27 fsci26 fsci25 fsci24 0dh fsci23 fsci22 fsci21 fsci20 fsci19 fsci18 fsci17 fsci16 0eh fsci15 fsci14 fsci13 fsci12 fsci11 fsci10 fsci9 fsci8 0fh fsci7 fsci6 fsci5 fsci4 fsci3 fsci2 fsci1 fsci0 10h civ25 civ24 civc1 civc0 paln civen 11h civ23 civ22 civ21 civ20 civ19 civ18 civ17 civ16 12h civ15 civ14 civ13 civ12 civ11 civ10 civ9 civ8 13h civ7 civ6 civ5 civ4 civ3 civ2 civ1 civ0 1ch m/s* mcp pcm xcm 1dh xcmd3 xcmd2 xcmd1 xcmd0 1eh goenb1 goenb0 gpiol1 gpiol0 reserved reserved poute poutp 1fh ibs des syo vsp hsp idf2 idf1 idf0 20h reserved xosc2 reserved dact3 dact2 dact1 dact0 sense 21h xosc1 xosc0 synco1 synco0 dacg1 dacg0 dacbp 22h shf2 shf1 shf0 bcoen bcop bco2 bco1 bco0 48h resetib resetdb rsa tstp1 tstp0 49h reserved reserved tv dacpd3 dacpd2 dacpd1 dacpd0 fpd 4ah vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 4bh did7 did6 did5 did4 did3 did2 did1 did0
201-0000-042 rev. 1.1, 9/29/2000 23 chrontel CH7012a non-macrovision control registers description display mode register symbol: dm address: 00h bits: 8 register dm provides programmable control of the CH7012 vga to tv display mode, including input resolution (ir[2:0]), video output standard (vos[1:0]), and scaling ratio (sr[2:0]). the mode of operation is determined according to table 10 below. for entries in which the output standard is shown as pal, pal-b,d,g,h,i,n,n c can be supported through proper selection of the chroma sub-carrier. for entries in which the output standard is shown as ntsc, ntsc- m,j and pal-m can be supported through proper selection of vos[1:0] and chroma sub-carrier. bit: 7 6 5 4 3 2 1 0 symbol: ir2 ir1 ir0 vos1 vos0 sr2 sr1 sr0 type: r/w r/w r/w r/w r/w r/w r/w r/w default: 0 1 1 0 1 0 1 0 table 10: display mode mode ir[2:0] vos [1:0] sr[2:0] input data format (active video) total pixels/line x total lines/frame output stan- dard [tv standard] scaling percent overscan pixel clock (mhz) 0 000 00 000 512x384 840x500 pal 5/4 -17 21.000000 1 000 00 001 512x384 840x625 pal 1/1 -33 26.250000 2 000 01 000 512x384 800x420 ntsc 5/4 0 20.139860 3 000 01 001 512x384 784x525 ntsc 1/1 -20 24.671329 4 001 00 000 720x400 1125x500 pal 5/4 -13 28.125000 5 001 00 001 720x400 1152x625 pal 1/1 -30 36.000000 6 001 01 000 720x400 945x420 ntsc 5/4 +4 23.790210 7 001 01 001 720x400 936x525 ntsc 1/1 -16 29.454545 8 010 00 000 640x400 1000x500 pal 5/4 -13 25.000000 9 010 00 001 640x400 1008x625 pal 1/1 -30 31.500000 10 010 01 000 640x400 840x420 ntsc 5/4 +4 21.146854 11 010 01 001 640x400 832x525 ntsc 1/1 -17 26.181819 12 010 01 010 640x400 840x600 ntsc 7/8 -27 30.209791 13 011 00 000 640x480 840x500 pal 5/4 +4 21.000000 14 011 00 001 640x480 840x625 pal 1/1 -17 26.250000 15 011 00 011 640x480 840x750 pal 5/6 -30 31.500000 16 011 01 001 640x480 784x525 ntsc 1/1 0 24.671329 17 011 01 010 640x480 784x600 ntsc 7/8 -13 28.195805 18 011 01 011 640x480 800x630 ntsc 5/6 -18 30.209790 19 100 01 001 720x480 882x525 ntsc 1/1 0 27.755245 20 100 01 010 720x480 882x600 ntsc 7/8 -13 31.720280 21 100 01 011 720x480 900x630 ntsc 5/6 -18 33.986015 22 101 00 001 720x576 882x625 pal 1/1 0 27.562500 23 101 00 011 720x576 900x750 pal 5/6 -18 33.750000 24 101 00 100 720x576 900x875 pal 5/7 -30 39.375000 25 110 00 001 800x600 944x625 pal 1/1 +4 29.500000 26 110 00 011 800x600 960x750 pal 5/6 -14 36.000000 27 110 00 100 800x600 960x875 pal 5/7 -27 42.000000 28 110 01 110 800x600 1040x700 ntsc 3/4 -6 43.636364 29 110 01 111 800x600 1064x750 ntsc 7/10 -14 47.832169 30 110 01 101 800x600 1040x840 ntsc 5/8 -22 52.363637 31 111 00 100 1024x768 1400x875 pal 5/7 -4 61.250000 32 111 00 101 1024x768 1400x1000 pal 5/8 -16 70.000000 33 111 00 110 1024x768 1400x1125 pal 5/9 -25 78.750000 34 111 01 101 1024x768 1160x840 ntsc 5/8 0 58.405595 35 111 01 110 1024x768 1160x945 ntsc 5/9 -10 65.706295 36 111 01 111 1024x768 1168x1050 ntsc 1/2 -20 73.510491 37 101 00 000 720x576 864x625 pal 1/1 0 13.500000 38 100 01 000 720x480 858x525 ntsc 1/1 0 13.500000
chrontel CH7012a 24 201-0000-042 rev. 1.1, 9/29/2000 flicker filter register symbol: ff address: 01h bits: 8 bits 1-0 of register ff control the filter used in the scaling and flicker reduction block applied to the non-text portion of the luminance signal as shown in table 12 below. bits 3-2 of register ff control the filter used in the scaling and flicker reduction block applied to the text portion of the luminance signal as shown in table 12 below. bits 5-4 of register ff control the filter used in the scaling and flicker reduction block applied to the chrominance signal as shown in table 13 below. a setting of ?11? applies a dot crawl reduction filter which can reduce the ?hanging dots? effect of an ntsc composite video signal when displayed on a tv with a comb filter. bit 6 of register ff controls the video output format. a value of ?0? generates composite and s-video outputs. a value of ?1? generates rgb outputs. table 11: video output standard selection vos[1:0] 00 01 10 11 output format pal ntsc pal-m ntsc-j bit: 7 6 5 4 3 2 1 0 symbol: vof cff1 cff0 yfft1 yfft0 yffnt1 yffnt0 type: r/w r/w r/w r/w r/w r/w r/w default: 0 1 0 0 1 1 1 table 12: luma flicker filter control yfft and yffnt flicker filter settings (lines) scaling ratio 00 01 10 11 5/4 2 3 3 3 1/1, 7/8, 5/6, 3/4, 5/7, 7/10 2 3 4 5 5/8 2 3 4 6 5/9 3 4 5 6 1/2 3 5 5 7 table 13: chroma flicker filter control cff flicker filter settings (lines) scaling ratio 00 01 10 11 5/4 2 3 3 3 1/1, 7/8, 5/6, 3/4, 5/7, 7/10 2 3 4 5 5/8 2 3 4 5 5/9 3 4 5 6 1/2 3 5 5 7
201-0000-042 rev. 1.1, 9/29/2000 25 chrontel CH7012a video bandwidth register symbol: vbw address: 02h bits: 8 bits 1-0 of register vbw control the filter used to limit the bandwidth of the luma signal in the cvbs output signal. a table of ?3db bandwidth values is given below. bits 3-2 of register vbw control the filter used to limit the bandwidth of the luma signal in the s-video output signal. a table of ?3db bandwidth values is given below. bit 4 of register vbw control the filter used to limit the bandwidth of the chroma signal in the cvbs and s-video output signals. a table of ?3db bandwidth values is given in table 14 below. bit 5 of register vbw controls the signal output on the cvbs pin. when this bit is low, the s-video luminance signal is output at both the s-video luminance pin and the cvbs pin. this enables the output of a black and white image on the composite output, thereby eliminating the degrading effects of the color signal (such as dot crawl and false colors), which is useful for viewing text with high accuracy. this also allows the output of either s-video or cvbs using just two dac?s. this is useful in situations where connector space is at a premium. bit: 7 6 5 4 3 2 1 0 symbol: vbid cfrb cvbwb cbw ysv1 ysv0 ycv1 ycv0 type: r/w r/w r/w r/w r/w r/w r/w r/w default: 0 0 0 1 1 1 1 0 table 14: video bandwidth mode cbw ysv[1:0] and ycv[1:0] 0 1 00 01 10 11 0 0.620 0.856 2.300 2.690 3.540 5.880 1 0.775 1.070 2.880 3.360 4.430 7.350 2 0.529 0.730 1.960 2.290 3.020 5.010 3 0.648 0.894 2.410 2.810 3.700 6.140 4 0.831 1.150 3.080 3.600 4.750 7.870 5 1.060 1.470 3.950 4.610 6.080 10.100 6 0.703 0.970 2.610 3.040 4.010 6.660 7 0.870 1.200 3.230 3.770 4.970 8.240 8 0.738 1.020 2.740 3.200 4.220 7.000 9 0.930 1.280 3.460 4.030 5.320 8.820 10 0.624 0.862 2.320 2.710 3.570 5.920 11 0.773 1.070 2.870 3.350 4.420 7.330 12 0.892 1.230 3.310 3.870 5.100 8.450 13 0.620 0.856 2.300 2.690 3.540 5.880 14 0.775 1.070 2.880 3.360 4.430 7.350 15 0.930 1.280 3.460 4.030 5.320 8.820 16 0.648 0.894 2.410 2.810 3.700 6.140 17 0.740 1.020 2.750 3.210 4.230 7.010 18 0.793 1.100 2.950 3.440 4.530 7.510 19 0.729 1.010 2.710 3.160 4.160 6.900 20 0.833 1.150 3.090 3.610 4.760 7.890 21 0.892 1.230 3.310 3.870 5.100 8.450 22 0.724 0.999 2.690 3.140 4.130 6.860 23 0.886 1.220 3.290 3.840 5.060 8.400 24 1.030 1.430 3.840 4.480 5.910 9.790 25 0.774 1.070 2.880 3.360 4.430 7.340
chrontel CH7012a 26 201-0000-042 rev. 1.1, 9/29/2000 bit 6 of register cvbwb controls whether the chroma sub-carrier free-runs, or is locked to the video signal. a ?1? causes the sub-carrier to lock to the tv vertical rate, and should be used when the civen bit (register 10h) is set to ?0?. a ?0? causes the sub-carrier to free-run, and should be used when the civen bit is set to ?1?. bit 7 of register cvbwb controls the vertical blanking interval defeat function. a ?1? in this register location forces the flicker filter to minimum filtering during the vertical blanking interval. a ?0? in this location causes the flicker filter to remain at the same setting inside and outside of the vertical blanking interval. text enhancement register symbol: te address: 03h bits: 6 bits 2-0 of register te control the text enhancement circuitry within the CH7012. a value of ?000? minimizes the enhancement feature, while a value of ?111? maximizes the enhancement. bits 5-3 of register te contain the msb values for the start of active video, horizontal position and vertical position controls. they are described in detail in the sav, hp and vp register descriptions. 26 0.945 1.310 3.510 4.100 5.400 8.960 27 1.100 1.520 4.100 4.780 6.300 10.400 28 0.859 1.190 3.190 3.720 4.910 8.140 29 0.942 1.300 3.500 4.080 5.380 8.920 30 1.030 1.420 3.830 4.470 5.890 9.770 31 0.804 1.110 2.990 3.480 4.590 7.620 32 0.919 1.270 3.410 3.980 5.250 8.710 33 1.030 1.430 3.840 4.480 5.910 9.790 34 0.767 1.060 2.850 3.320 4.380 7.260 35 0.862 1.190 3.200 3.740 4.930 8.170 36 0.965 1.330 3.580 4.180 5.510 9.140 37 0.709 0.979 2.630 3.070 4.050 6.720 38 0.466 0.643 1.730 2.020 2.660 4.410 bit: 7 6 5 4 3 2 1 0 symbol: sav8 hp8 vp8 te2 te1 te0 type: r/w r/w r/w r/w r/w r/w default: 0 0 0 1 0 1 table 14: video bandwidth
201-0000-042 rev. 1.1, 9/29/2000 27 chrontel CH7012a start of active video register symbol: sav address: 04h bits: 8 register sav controls the delay, in pixel increments, from leading edge of horizontal sync to start of active video. the entire bit field sav[8:0] is comprised of this register sav[7:0], plus the msb value contained in the text enhancement register, bit sav8. this is decoded as a whole number of pixels, which can be set anywhere between 0 and 511 pixels. therefore, in any 2x clock mode the number of 2x clocks from the leading edge of sync to the first active data must be a multiple of two clocks. horizontal position register symbol: hp address: 05h bits: 8 register hp is used to shift the displayed tv image in a horizontal direction ( left or right) to achieve a horizontally centered image on screen. the entire bit field, hp[8:0], is comprised of this register hp[7:0] plus the msb value contained in the text enhancement register, bit hp8. increasing values move the displayed image position right, and decreasing values move the image position left. vertical position register symbol: vp address: 06h bits: 8 register vp is used to shift the displayed tv image in a vertical direction ( up or down) to achieve a vertically centered image on screen. the entire bit field, vp[8:0], is comprised of this register hp[7:0] plus the msb value contained in the text enhancement register, bit vp8. the value represents the tv line number (relative to the vga vertical sync) used to initiate the generation and insertion of the tv vertical interval (i.e. the first sequence of equalizing pulses). increasing values delay the output of the tv vertical sync, causing the image position to move up on the tv screen. decreasing values, therefore, move the image position down. each increment moves the image position by one tv lines (approximately 2 input lines). the maximum value that should be programmed into the vp[8:0] value is the number of tv lines per field minus one half (262 or 312). when panning the image up, the number should be increased until (tvlpf-1/2) is reached, the next step should be to reset the register to zero. when panning the image down the screen, decrement the vp[8:0] value until the value zero is reached. the next step should set the register to tvlpf-1/2, and then decrement for further changes. bit: 7 6 5 4 3 2 1 0 symbol: sav7 sav6 sav5 sav4 sav3 sav2 sav1 sav0 type: r/w r/w r/w r/w r/w r/w r/w r/w default: 0 1 0 1 0 0 0 0 bit: 7 6 5 4 3 2 1 0 symbol: hp7 hp6 hp5 hp4 hp3 hp2 hp1 hp0 type: r/w r/w r/w r/w r/w r/w r/w r/w default: 0 1 0 1 0 0 0 0 bit: 7 6 5 4 3 2 1 0 symbol: vp7 vp6 vp5 vp4 vp3 vp2 vp1 vp0 type: r/w r/w r/w r/w r/w r/w r/w r/w default: 0 0 0 0 0 0 0 0
chrontel CH7012a 28 201-0000-042 rev. 1.1, 9/29/2000 black level register symbol: bl address: 07h bits: 8 register bl controls the black level. the luminance data is added to this black level, which must be set between 51 and 208. when the input data format is zero through three the default values are 131 for ntsc and pal-m, 110 for pal and 102 for ntsc-j. when the input data format is four the default values are 112 for ntsc and pal-m, 94 for pal and 88 for ntsc-j. contrast enhancement register symbol: ce address: 08h bits: 3 bits 2-0 of register ce control contrast enhancement feature of the CH7012, according to the figure below. a setting of ?0? results in reduced contrast, a setting of ?1? leaves the image contrast unchanged, and values beyond ?1? result in increased contrast. figure 16: contrast enhancement diagram bit: 7 6 5 4 3 2 1 0 symbol: bl7 bl6 bl5 bl4 bl3 bl2 bl1 bl0 type: r/w r/w r/w r/w r/w r/w r/w r/w default: 1 0 0 0 0 0 1 1 bit: 7 6 5 4 3 2 1 0 symbol: ce2 ce1 ce0 type: r/w r/w r/w default: 0 1 1 32 36 104 172 240 308 376 444 512 32 36 104 172 240 308 376 444 512 < > yout i n 256 yin n
201-0000-042 rev. 1.1, 9/29/2000 29 chrontel CH7012a tv pll control register symbol: tpc address: 09h bits: 5 bit 0 of register tpc controls the tv pll loop filter capacitor. a recommended listing of pllcap setting versus mode is listed in table 15 below. bit 1 of register tpc should be left at the default value. bits 4-2 of register tpc contain the msb values for the tv pll divider ratio?s. these controls are described in detail in the pllm and plln register descriptions. bit 5 of register tpc controls the input latch bias current. a value of tbd is recommended. bits 7-6 of register tpc control the memory sense amp reference level. the default value is recommended. bit: 7 6 5 4 3 2 1 0 symbol: mem2 mem1 ibi n9 n8 m8 pllcpi pllcap type: r/w r/w r/w r/w r/w r/w r/w r/w default: 1 0 0 0 0 0 0 0 table 15: pllcap setting vs display mode mode pllcap value mode pllcap value 0 1 20 0 1 1 21 0 2 0 22 1 3 0 23 1 4 1 24 1 5 1 25 0 6 0 26 1 7 1 27 1 8 0 28 1 9 1 29 0 10 0 30 1 11 1 31 1 12 0 32 1 13 1 33 1 14 1 34 0 15 1 35 0 16 0 36 0 17 0 37 1 18 0 38 1 19 0
chrontel CH7012a 30 201-0000-042 rev. 1.1, 9/29/2000 tv pll m value register symbol: pllm address: 0ah bits: 8 register pllm controls the division factor applied to the 14.31818mhz frequency reference clock before it is input to the tv pll phase detector when the CH7012 is operating in master clock mode. the entire bit field, m[8:0], is comprised of this register m[7:0] plus the msb value contained in the tv pll control register, bit m8. in slave clock mode, an external pixel clock is used instead of the 14.31818mhz frequency reference, and the division factor is determined by the xcm value in register 1dh. a table of values versus display mode is given following the plln register description. tv pll n value register symbol: plln address: 0bh bits: 8 register plln controls the division factor applied to the vco output before being applied to the pll phase detector, when the CH7012 is operating in master clock mode. the entire bit field, n[9:0], is comprised of this register n[7:0] plus the msb values contained in the tv pll control register, bits n9 and n8. in slave clock mode, the value of ?n? is internally set to 1. the pixel clock generated in master clock modes is calculated according to the equation fpixel = fref * [(n+2) / (m+2)]. when using a 14.31818mhz frequency reference, the required m and n values for each mode are shown in table 16 below: bit: 7 6 5 4 3 2 1 0 symbol: m7 m6 m5 m4 m3 m2 m1 m0 type: r/w r/w r/w r/w r/w r/w r/w r/w default: 0 0 1 1 1 1 1 1 bit: 7 6 5 4 3 2 1 0 symbol: n7 n6 n5 n4 n3 n2 n1 n0 type: r/w r/w r/w r/w r/w r/w r/w r/w default: 0 1 1 1 1 1 1 0 table 16: tv pll m and n values vs display mode mode vga resolution, tv standard, scaling ratio n 10- bits m 9-bits mode vga resolution, tv standard, scaling ratio n 10- bits m 9-bits 0 512x384, pal, 5:4 20 13 20 720x480, ntsc, 7:8 142 63 1 512x384, pal, 1:1 9 4 21 720x480, ntsc, 5:6 214 89 2 512x384, ntsc, 5:4 126 89 22 720x480, pal, 1:1 75 38 3 512x384, ntsc, 1:1 110 63 23 720x480, pal, 5:6 31 12 4 720x400, pal, 5:4 53 26 24 720x480, pal, 5:7 9 2 5 720x400, pal, 1:1 86 33 25 800x600, pal, 1:1 647 313 6 720x400, ntsc, 5:4 106 63 26 800x600, pal, 5:6 86 33 7 720x400, ntsc, 1:1 70 33 27 800x600, pal, 5:7 42 13 8 640x400, pal, 5:4 108 61 28 800x600, ntsc, 3:4 62 19 9 640x400, pal, 1:1 9 3 29 800x600, ntsc, 7:10 302 89 10 640x400, ntsc, 5:4 94 63 30 800x600, ntsc, 5/8 126 33 11 640x400, ntsc, 1:1 62 33 31 1024x768, pal, 5:7 75 16 12 640x400, ntsc, 7:8 190 89 32 1024x768, pal, 5:8 42 7 13 640x480, pal, 5:4 20 13 33 1024x768, pal, 5:9 20 2 14 640x480, pal, 1:1 9 4 34 1024x768, ntsc, 5:8 565 137 15 640x480, pal, 5:6 9 3 35 1024x768, ntsc, 5:9 333 71 16 640x480, ntsc, 1:1 110 63 36 1024x768, ntsc, 1:2 917 177
201-0000-042 rev. 1.1, 9/29/2000 31 chrontel CH7012a sub-carrier value register symbol: fsci address: 0ch ? 0fh bits: 8 each registers fsci contain a 32-bit value which is used as an increment value for the rom address generation circuitry when civen=0. the bit locations are specified as follows: register contents 0ch fsci[31:24] 0dh fsci[23:16] 0eh fsci[15:8] 0fh fsci[7:0] when the CH7012 is used in the master clock mode, the tables below should be used to set the fsci registers. when using these values, the civen bit in register 10h should be set to ?0?, and the cfrb bit in register 02h should be set to ?1?. 17 640x480, ntsc, 7:8 126 63 37 720x576, pal, 1:1 31 33 18 640x480, ntsc, 5:6 190 89 38 720x480, ntsc, 1:1 31 33 19 720x480, ntsc, 1:1 124 63 bit: 7 6 5 4 3 2 1 0 symbol: fsci# fsci# fsci# fsci# fsci# fsci# fsci# fsci# type: r/w r/w r/w r/w r/w r/w r/w r/w default: table 17: fsci values (525-line tv-out modes) mode ntsc ?normal dot crawl? ntsc ?no dot crawl? pal-m ?normal dot crawl? 2 763,363,328 763,366,524 762,524,467 3 623,153,737 623,156,346 622,468,953 6 574,429,782 574,432,187 573,798,541 7 463,962,517 463,964,459 463,452,668 10 646,233,505 646,236,211 645,523,358 11 521,957,831 521,960,019 521,384,251 12 452,363,454 452,365,347 451,866,351 16 623,153,737 623,156,346 622,468,953 17 545,259,520 545,261,803 544,660,334 18 508,908,885 508,911,016 508,349,645 19 553,914,433 553,916,752 553,305,736 20 484,675,129 484,677,158 484,142,519 21 452,363,454 452,365,347 451,866,351 28 469,762,048 469,764,015 469,245,826 29 428,554,851 428,556,645 428,083,911 30 391,468,373 391,470,012 391,038,188 34 526,457,468 526,459,671 525,878,943 35 467,962,193 467,964,152 467,447,949 36 418,281,276 418,283,027 417,821,626 38 569,408,543 569,410,927 568,782,819 table 16: tv pll m and n values vs display mode
chrontel CH7012a 32 201-0000-042 rev. 1.1, 9/29/2000 civ control register symbol: civc address: 10h bits: 6 bit 0 of register civc controls whether the fsci value is used to set the sub-carrier frequency, or the automatically calculated (civ) value. when the civen value is 1, the number calculated and present at the civ registers will automatically be used as the increment value for sub-carrier generation. whenever this bit is set to 1, the cfrb bit should be set to 0. bit 1 of register civc forces the civ algorithm to generate the pal-n (argentina) sub-carrier frequency when it is set to ?1?. when this bit is set to ?0?, the vos[1:0] value is used by the civ algorithm to determine which sub- carrier frequency to generate. bits 3-2 of register civc control the hysteresis circuit which is used to calculate the civ value. the default value should be used. bits 5-4 of register civc contain the msb values for the calculated increment value (civ) readout. this is described in detail in the civ register description. table 18: fsci values (625-line tv-out modes) mode pal ?normal dot crawl? pal-n ?normal dot crawl? 0 806,021,060 651,209,077 1 644,816,848 520,967,262 4 601,829,058 486,236,111 5 470,178,951 379,871,962 8 677,057,690 547,015,625 9 537,347,373 434,139,385 13 806,021,060 651,209,077 14 644,816,848 520,967,262 15 537,347,373 434,139,385 22 690,875,194 558,179,209 23 564,214,742 455,846,354 24 483,612,636 390,725,446 25 645,499,916 521,519,134 26 528,951,320 427,355,957 27 453,386,846 366,305,106 31 621,787,675 502,361,288 32 544,064,215 439,566,127 33 483,612,636 390,725,446 37 705,268,427 569,807,942 bit: 7 6 5 4 3 2 1 0 symbol: civ25 civ24 civc1 civc0 paln civen type: r/w r/w r/w r/w r/w r/w default: 0 0 0 0 0 1
201-0000-042 rev. 1.1, 9/29/2000 33 chrontel CH7012a calculated increment value register symbol: civ address: 11h ? 13h bits: 8 each registers civ contain the value that was calculated by the CH7012 as the sub-carrier increment value. the entire bit field, civ[25:0], is comprised of these three registers plus the msb values contained in the civ control register, bits civ25 and civ24. this value is used when the civen bit is set to ?1?. the bit locations are specified below. register contents 10h civ[25:24] 11h civ[23:16] 12h civ[15:8] 13h civ[7:0] clock mode register symbol: cm address: 1ch bits: 4 bit 0 of register cm signifies the xclk frequency. a value of ?0? is used when the xclk is at the pixel frequency (duel edge clocking mode) and a value of ?1? is used when the xclk is twice the pixel frequency (single edge clocking mode). bit 1 of register cm controls the p-out clock frequency. a value of ?0? generates a clock output at the pixel frequency, while a value of ?1? generates a clock at twice the pixel frequency. bit 2 of register cm controls the phase of the xclk clock input to the CH7012. a value of ?1? inverts the xclk signal at the input of the device. this control is used to select which edge of the xclk signal to use for latching input data. bit 3 of register cm controls whether the device operates in master or slave clock mode. in master mode (m/s* = ?1?), the 14.31818mhz clock is used as a frequency reference in the tv pll, and the m and n values are used to determine the tv pll?s operating frequency. in slave mode (m/s* = ?0?) the xclk input is used as a reference to the tv pll. the m and n tv pll divider values are forced to one. bit: 7 6 5 4 3 2 1 0 symbol: civ# civ# civ# civ# civ# civ# civ# civ# type: r/w r/w r/w r/w r/w r/w r/w r/w default: 0 0 0 0 0 0 0 0 bit: 7 6 5 4 3 2 1 0 symbol: m/s* mcp pcm xcm type: r/w r/w r/w r/w default: 0 0 0 0
chrontel CH7012a 34 201-0000-042 rev. 1.1, 9/29/2000 input clock register symbol: ic address: 1dh bits: 8 bits 3-0 of register ic controls the delay applied to the xclk signal before latching input data. gpio control register symbol: gpio address: 1eh bits: 8 bit 0 of register gpio controls the polarity of the p-out signal. a value of ?0? does not invert the clock at the output pad. bit 1 of register gpio enables the p-out signal. a value of ?1? drives the p-out clock signal out of the p-out pin. a value of ?0? disables the p-out signal. bits 5-4 of register gpio control the gpio pins. when the corresponding goenb bits are low, these register values are driven out of the corresponding gpio pins. when the corresponding goenb bits are high, these register values can be read to determine the level forced into the corresponding gpio pins. bits 7-6 of register gpio control the direction of the gpio pins. a value of ?1? sets the corresponding gpio pin to an input, and a value of ?0? sets the corresponding pin to an output. input data format register symbol: idf address: 1fh bits: 8 bits 2-0 of register idf select the input data format. see the input interface on page 8 for a listing of available formats. bit 3 of register idf controls the horizontal sync polarity. a value of ?0? defines the horizontal sync to be active low, and a value of ?1? defines the horizontal sync to be active high. bit: 7 6 5 4 3 2 1 0 symbol: reserved reserved reserved reserved xcmd3 xcmd2 xcmd1 xcmd0 type: r/w r/w r/w r/w r/w r/w r/w r/w default: 1 0 0 0 1 0 0 0 bit: 7 6 5 4 3 2 1 0 symbol: goenb1 goenb0 gpiol1 gpiol0 reserved reserved poute poutp type: r/w r/w r/w r/w r/w r/w r/w r/w default: 1 1 0 0 0 0 0 0 bit: 7 6 5 4 3 2 1 0 symbol: ibs des syo vsp hsp idf2 idf1 idf0 type: r/w r/w r/w r/w r/w r/w r/w r/w default: 0 0 0 0 0 0 0 0
201-0000-042 rev. 1.1, 9/29/2000 35 chrontel CH7012a bit 4 of register idf controls the vertical sync polarity. a value of ?0? defines the vertical sync to be active low, and a value of ?1? defines the vertical sync to be active high. bit 5 of register idf controls the sync direction. a value of ?0? defines sync to be input to the CH7012, and a value of ?1? defines sync to be output from the CH7012. the CH7012 can only output sync signals when operating as a vga to tv encoder. bit 6 of register idf signifies when the CH7012 is to decode embedded sync signals present in the input data stream instead of using the h and v pins. this feature is only available for input data format four. a value of ?0? selects the h and v pins to be used as the sync inputs, and a value of ?1? selects the embedded sync signal. bit 7 of register idf selects the input buffer used for the data, sync and clock input pins. connection detect register symbol: cd address: 20h bits: 6 the connection detect register provides a means to sense the connection of a tv to the four dac outputs. the status bits, dact[3:0] correspond to the termination of the four dac outputs. however, the values contained in these status bits are not valid until a sensing procedure is performed. use of this register requires a sequence of events to enable the sensing of outputs, then reading out the applicable status bits. the detection sequence works as follows: 1) set the power management register to enable all dac?s. 2) set the sense bit to a 1. this forces a constant output from the dac?s. note that during sense = 1, these 4 analog outputs are at steady state and no tv synchronization pulses are asserted. 3) reset the sense bit to 0. this triggers a comparison between the voltage present on these analog outputs and the reference value. during this step, each of the four status bits corresponding to individual dac outputs will be set if they are connected. 4) read the status bits. the status bits, dact[3:0] now contain valid information which can be read to determine which outputs are connected to a tv. again, a ?1? indicates a valid connection, a ?0? indicates an unconnected output. bit 6 of register cd contains the msb value for the crystal oscillator adjustment. this control is described in detail in the dc register description (register 21h). bit: 7 6 5 4 3 2 1 0 symbol: reserved xosc2 reserved dact3 dact2 dact1 dact0 sense type: r/w r/w r r r r r r/w default: 0 0 0 0 0 0 0 0
chrontel CH7012a 36 201-0000-042 rev. 1.1, 9/29/2000 dac control register symbol: dc address: 21h bits: 6 bit 0 of register dc selects the dac bypass mode. a value of ?1? outputs the incoming data directly at the dac[2:0] outputs. bits 2-1 of register dc control the dac gain. dacg0 should be set low for ntsc and pal-m video standards, and high for pal and ntsc-j video standards. dacg1 should be low when the input data format is rgb (idf = 0-3), and high when the input data format is ycrcb (idf = 4). bits 4-3 of register dc select the signal to be output from the c/h sync pin according to table 19 below. bits 7-6 of register dc controls the crystal oscillator. the default value is recommended. buffered clock output register symbol: bco address: 22h bits: 8 bits 2-0 of register bco select the signal output at the bco pin, according to table 20 below: bit: 7 6 5 4 3 2 1 0 symbol: xosc1 xosc0 synco1 synco0 dacg1 dacg0 dacbp type: r/w r/w r/w r/w r/w r/w r/w default: 0 0 0 0 0 0 0 table 19: composite / horizontal sync output synco[1:0] c/h sync output 00 no output 01 vga horizontal sync 10 tv composite sync 11 tv horizontal sync bit: 7 6 5 4 3 2 1 0 symbol: shf2 shf1 shf0 bcoen bcop bco2 bco1 bco0 type: r/w r/w r/w r/w r/w r/w r/w r/w default: 0 0 0 0 0 0 0 0 table 20: bco output signal bco[2:0] buffered clock output bco[2:0] buffered clock output 000 the 14mhz crystal 100 (for test use only) 001 (for test use only) 101 (for test use only) 010 vco divided by k3 110 vga vertical sync 011 field id 111 tv vertical sync
201-0000-042 rev. 1.1, 9/29/2000 37 chrontel CH7012a bit 3 of register bco selects the polarity of the bco output. a value of ?1? does not invert the signal at the output pad. bit 4 of register bco enables the bco output. when bcoen is high, the bco pin will output the selected signal. when bcoen is low, the bco pin will be held in tri-state mode. bits 7-5 of register bco select the k3 divider, according to table 21 below. test pattern register symbol: tstp address: 48h bits: 5 bits 1-0 of register tstp control the test pattern generation block. the pattern generated is determined by table 22 below. bit 2 of register tstp is a test control, and should be left at the default value. bit 3 of register tstp controls the datapath reset signal. a value of ?0? holds the datapath in a reset condition, while a value of ?1?, places the datapath in normal mode. the datapath is also reset at power on by an internally generated power on reset signal. bit 4 of register tstp controls the serial port reset signal. a value of ?0? holds the serial port registers in a reset condition, while a value of ?1?, places the serial port registers in normal mode. the serial port registers are also reset at power on by an internally generated power on reset signal. table 21: k3 selection shf[2:0] k3 000 2.5 001 3.0 010 3.5 011 4.0 100 4.5 101 5.0 110 6.0 111 7.0 bit: 7 6 5 4 3 2 1 0 symbol: resetib resetdb rsa tstp1 tstp0 type: r/w r/w r/w r/w r/w default: 1 1 0 0 0 table 22: test pattern control tstp[1:0] buffered clock output 00 no test pattern ? input data is used 01 color bars 1x horizontal luminance ramp
chrontel CH7012a 38 201-0000-042 rev. 1.1, 9/29/2000 power management register symbol: pm address: 49h bits: 8 register pm controls which circuitry within the CH7012 is operating, according to table 23 below. version id register symbol: vid address: 4ah bits: 8 register vid is a read only register containing the version id number of the CH7012. device id register symbol: did address: 4bh bits: 8 register did is a read only register containing the device id number of the CH7012. bit: 7 6 5 4 3 2 1 0 symbol: reserved reserved tv dacpd3 dacpd2 dacpd1 dacpd0 fpd type: r/w r/w r/w r/w r/w r/w r/w r/w default: 0 0 0 0 0 0 0 1 table 23: power management circuit block is operational when vga to tv encoder tv = 1 & fpd = 0 dac 3 dacpd3 = 0 & fpd = 0 dac 2 dacpd2 = 0 & fpd = 0 dac 1 dacpd1 = 0 & fpd = 0 dac 0 dacpd0 = 0 & fpd = 0 tv pll, p-out and bco pins fpd = 0 bit: 7 6 5 4 3 2 1 0 symbol: vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 type: r r r r r r r r default: 0 0 0 0 0 0 1 0 bit: 7 6 5 4 3 2 1 0 symbol: did7 did6 did5 did4 did3 did2 did1 did0 type: r r r r r r r r default: 0 0 0 1 0 1 1 0
201-0000-042 rev. 1.1, 9/29/2000 39 chrontel CH7012a electrical specifications notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated under the normal operating condition of this specification is not recommended. exposure to absolute maximum rating conditions for extended periods my affect reliability. 2. the device is fabricated using high-performance cmos technology. it should be handled as an esd sensitive device. voltage on any signal pin that exceeds the power supply voltages by more than 0. 5v can induce destructive latch. table 24. absolute maximum ratings symbol description min typ max units dvdd, avdd, tvdd, vdd relative to gnd - 0.5 5.0 v input voltage of all digital pins 1 gnd - 0.5 vdd + 0.5 v t sc analog output short circuit duration indefinite sec t amb ambient operating temperature - 55 85 c t s t o r storage temperature - 65 150 c t j junction temperature 150 c t v ps vapor phase soldering (one minute) 220 c table 25. recommended operating conditions symbol description min typ max units v dd dac power supply voltage 3.1 3.3 3.6 v avdd analog supply voltage 3.1 3.3 3.6 v dvdd digital supply voltage 3.1 3.3 3.6 v dvddv digital supply voltage (p-out pin) 1.1 1.8 3.6 v r l output load to dac outputs 37.5 w table 26. electrical characteristics (operating conditions: t a = 0 o c - 70 o c, vdd, avdd, dvdd, tvdd = 3.3v 5%) symbol description min typ max units video d/a resolution 10 10 10 bits full scale output current 33.89 ma video level error 10 % i vdd 4 dac?s enabled 130 145 ma i vdd 3 dac?s enabled 100 110 ma i avdd 5 7 ma i dvdd 85 150 ma dvddv (1.8v) curent (15pf load) 4 ma
chrontel CH7012a 40 201-0000-042 rev. 1.1, 9/29/2000 table 27. digital inputs / outputs note: symbol description test condition min typ max unit v sdol sd output low voltage iol = 2.0 ma 0.4 v v iicih sd input high voltage 2.7 dvdd + 0.5 v v iicil sd input low voltage gnd-0.5 1.4 v v dataih d[0-11] input high voltage vref-0.25 dvdd+0.5 v v datail d[0-11] input low voltage gnd-0.5 vref+0.25 v v p-outoh p-out output high voltage iol = - 400 m a dvddv-0.2 v v p-outol p-out output low voltage iol = 3.2 ma 0.2 v v iic - refers to serial port pins sd and sc. v data - refers to all digital pixel and clock inputs. v sd - refers to serial port pin sd as an output. v p-out - refers to pixel data output time - grapics.
201-0000-042 rev. 1.1, 9/29/2000 41 chrontel CH7012a mechanical package information
chrontel 2210 o?toole avenue san jose, ca 95131-1326 tel: (408) 383-9328 fax: (408) 383-9338 www.chrontel.com e-mail: sales@chrontel.com 1998 chrontel, inc. all rights reserved. chrontel products are not authorized for and should not be used within life support systems or nuclear facility applications wit hout the specific written consent of chrontel. life support systems are those intended to support or sustain life and whose failure to p erform when used as directed can reasonably expect to result in personal injury or death. chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. we provi de no warranty for the use of our products and assume no liability for errors contained in this document. printed in the u.s.a. ordering information part number package type number of pins voltage supply CH7012a-t lqfp 64 3.3v 42 201-0000-042 rev. 1.1, 9/29/2000 chrontel

▲Up To Search▲

Price & Availability of CH7012

	To Download CH7012 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .